Structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage

ABSTRACT

The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.

RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/164,378, filed Nov. 21, 2005.

FIELD OF THE INVENTION

The present invention relates to a semiconductor structure and a methodof fabricating the same. More particularly, the present inventionrelates to a semiconductor structure that has a low-resistance extensionconnection (on the order of less than 50 ohms/square, preferably fromabout 2 to about 30 ohms/square; prior art values are typically fromabout 50 to about 500 ohms/square) between the channel of a metal oxidesemiconductor field effect transistor (MOSFET) and silicidedsource/drain regions with an independence from extension implants anddevice overlap (i.e., Miller) capacitance. The present invention alsoprovides a method of fabricating such a semiconductor structure in whichportions of the source/drain extension regions located between thesilicided source/drain regions and the channel are selectively platedwith a metallic or intermetallic material.

BACKGROUND OF THE INVENTION

Field effect transistors (FETs) are the basic building block of today'sintegrated circuit. Such transistors can be formed in conventional bulksubstrates (such as silicon) or in semiconductor-on-insulator (SOI)substrates

State of the art metal oxide semiconductor (MOS) transistors arefabricated by depositing a gate stack material over a gate dielectricand a substrate. Generally, the MOS transistor fabrication processimplements lithography and etching processes to define the conductive,e.g., poly-Si, Si, gate structures. The gate structure and substrate arethermally oxidized, and, after this, source/drain extensions are formedby implantation. Sometimes the implant is performed using a spacer tocreate a specific distance between the gate and the implanted junction.In some instances, such as in the manufacture of an n-FET device, thesource/drain extensions for the n-FET device are implanted with nospacer. For a p-FET device, the source/drain extensions are typicallyimplanted with a spacer present. A thicker spacer is typically formedafter the source/drain extensions have been implanted. The deepsource/drain implants are then performed with the thick spacer present.High temperature anneals are performed to activate the junctions afterwhich the source/drain and top portion of the gate are generallysilicided. Silicide formation typically requires that a refractory metalbe deposited on a Si-containing substrate followed by a high temperaturethermal anneal process to produce the silicide material. The silicideprocess forms low resistivity contacts to the deep source/drain regionsand the gate conductor.

In order to be able to make integrated circuits (ICs), such as memory,logic, and other devices, of higher integration density than currentlyfeasible, one has to find a way to further downscale the dimensions offield effect transistors (FETs), such as metal oxide semiconductors. Thedownscaling of transistor dimensions allows for improved performance aswell as compactness, but such downscaling has some device degradingeffects. Generational improvements for high performance MOS devices areobtained by decreasing the transistor line width, reducing the gateoxide thickness, and decreasing the source/drain extension resistance.Smaller transistor line width results in less distance between thesource and the drain. This results in faster switching speeds forcomplementary metal oxide semiconductor (CMOS) circuits. However, as thetransistor line width gets smaller, the overall area available forsilicidation is reduced. This means that as transistor line widthshrinks, line resistance (i.e., series resistance) is increased.Increased line resistance causes degradation in device performance.

Source/drain extension resistance is another important performancefactor. Drive currents may be increased by reducing source/drainextension resistance. Increasing the source/drain extension dose leadsto lower resistance but has an undesirable side effect of increasing thejunction depth.

As such, there is a need for providing a semiconductor structure havinga low-resistance extension connection between the channel and thesilicided source/drain regions with an independence from extensionimplants and device overlap (i.e., Miller) capacitance. Millercapacitance, which can also be referred to as the gate-drain orgate-source capacitance, increases the capacitance by a factor relatedto the voltage gain of a transistor.

SUMMARY OF THE INVENTION

The present invention provides a method in which a low-resistanceconnection between the device channel and silicided source/drain regionsis provided that has an independence from the extension ion implantprocess as well as device overlap capacitance. The method of the presentinvention broadly includes selectively removing outer spacers of an MOSstructure and then selectively plating a metallic or intermetallicmaterial on exposed portions of a semiconductor substrate that werepreviously protected by the outer spacers. The exposed portions arelocated between the silicided source/drain regions and the channelregion (or the edge of the gate conductor).

In general terms, the method of the present invention comprises:

providing a MOS structure that at includes at least one gate regionlocated on a surface of a semiconductor substrate, said at least onegate region comprising source/drain regions and source/drain extensionregions in said semiconductor substrate that are separated by a channelregion, a gate dielectric and a gate conductor located above saidchannel region, an offset spacer located on sidewalls of at least saidgate conductor and an outer spacer adjacent to said offset spacer andsilicide contacts located atop the source/drain regions adjacent saidouter spacer;

removing said outer spacer to expose a surface portion of thesemiconductor substrate including said source/drain extension regions;and

selectively plating a metallic or intermetallic material on said exposedsurface portion of said semiconductor substrate including saidsource/drain extension regions.

In addition to the method, the present invention also relates to asemiconductor structure that is formed utilizing the method describedabove. In broad terms, the semiconductor structure includes alow-resistance connection between the silicided source/drain regions andthe channel region which includes a selectively plated metallic orintermetallic material. By “low-resistance” it is meant a connectionthat has a resistivity on the order of less than 50 ohms/square, withabout 2 to about 30 ohms/square being more typical. In the prior art,the resistance is typically about 50 to about 500 ohms/square, thus thepresent invention represents an improvement over prior art structures.

In general terms, the semiconductor structure comprises:

a semiconductor substrate including source/drain extension regions and achannel region located between said source/drain extension regions;

a gate dielectric and a gate conductor located above the channel regionand positioned on a surface of said semiconductor substrate, said gatedielectric and said gate conductor having vertical edges that arecovered by an offset spacer; and

silicide source/drain contacts, wherein said silicide source/draincontacts are spaced apart from said channel region by a metallic orintermetallic material that is located on the surface of saidsemiconductor substrate including said source/drain extension regions.

The term “silicided source/drain contacts” is used herein to denote theportions of the source/drain regions that have been silicided by aconventional salicidation process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial representation (through a cross sectional view)depicting an initial MOS structure that is used in the presentinvention.

FIG. 2 is a pictorial representation (through a cross sectional view)depicting the MOS structure of FIG. 1 after removing the outer spacerfrom the structure.

FIG. 3 is a pictorial representation (through a cross sectional view)depicting the MOS structure of FIG. 2 after performing a selectiveplating process in which a metallic or intermetallic material is formedat least over exposed portions of the source/drain extension regions.

FIG. 4 is a pictorial representation (through a cross sectional view)depicting the MOS structure of FIG. 3 after forming an optionalstress-inducing liner over the structure.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides a method for fabricating asemiconductor structure having reduced extension resistance and theresultant structure formed by the method, will now be described ingreater detail by referring to the following discussion and drawingsthat accompany the present application. It is noted that the drawings ofthe present application are provided for illustrative purposes and, assuch, they are not drawn to scale.

FIG. 1 illustrates an initial MOS structure 10 that is employed in thepresent invention. As illustrated, the initial MOS structure 10 includesa semiconductor substrate 12 that has at least one gate region 14. Theat least one gate region 14 includes source/drain regions 16,source/drain extension regions 18, a channel region 20, a gatedielectric 22 and a gate conductor 24. As shown, the source/drainextension regions 18 are separated from each other by the channel region20. Also, as shown, the gate dielectric 22 and the gate conductor 24 arelocated atop the channel region 20 on a surface of the semiconductorsubstrate 12. The gate region 14 also includes a pair of spacers,including an inner (i.e., offset) spacer 26 and an outer spacer 28. Theinner spacer 26 is located on sidewalls of at least the gate conductor24. The at least one gate region 14 also includes a silicide region 30located atop the source/drain regions 16 and an optional silicide region32 atop the gate conductor 24. The initial structure 10 also includestrench isolation regions 34 that are located in the semiconductorsubstrate 12.

It is noted that the at least one gate region 14 is provided forillustrative purposes and thus the present invention is not limited toonly a single gate region. Instead, the present invention works when thesubstrate includes a plurality of gate regions. The plurality of gateregions may have the same or different conductivities, i.e., n-FETs,p-FETs or a combination of n-FETs and p-FETs.

The initial structure 10 is formed utilizing conventional CMOSprocessing techniques and materials well-known in the art. For example,the semiconductor substrate 12 of the initial structure 10 comprises anysemiconducting material including, but not limited to: Si, Ge, SiGe,SiC, SiGeC, Ga, GaAs, InAs, InP and all other III/V compoundsemiconductors. Semiconductor substrate 12 may also comprise an organicsemiconductor or a layered semiconductor such as Si/SiGe, or asemiconductor-on-insulator (SOI). In some embodiments of the presentinvention, it is preferred that the semiconductor substrate 12 becomposed of a Si-containing semiconductor material, i.e., asemiconductor material that includes silicon. The semiconductorsubstrate 12 may be doped, undoped or contain doped and undoped regionstherein.

When SOI substrates are used such as shown in FIG. 1, the SOI substrateincludes a top semiconductor layer 12A, an insulating layer 12B, and abottom semiconductor layer (not shown in the drawings). The insulatinglayer 12B, which comprises a crystalline or non-crystalline oxide ornitride, separates the top semiconductor layer from the bottomsemiconductor layer. When SOI substrates are used, the trench isolationregions 34 may, in some embodiments, extend down to the surface of theburied insulating layer that separates the top semiconductor layer fromthe bottom semiconductor layer. In yet other embodiments, the trenchisolation regions 34 do not extend to the surface of the buriedinsulating layer.

The semiconductor substrate 12 may also include a first doped (n- or p-)region, and a second doped (n- or p-) region. For clarity, the dopedregions are not specifically labeled in the drawings of the presentapplication. The first doped region and the second doped region may bethe same, or they may have different conductivities and/or dopingconcentrations. These doped regions are known as “wells”.

It is also noted that the semiconductor substrate 12 may be strained,unstrained or contain strained regions and unstrained regions therein.The semiconductor substrate 12 may also have a single crystalorientation or alternatively, the substrate 12 may be a hybridsemiconductor substrate that has surfaces having differentcrystallographic orientations.

Trench isolation regions 34 are formed in the semiconductor substrate 12prior to well formation utilizing conventional processes well known tothose skilled in the art. The trench isolation regions 34 are typicallyformed utilizing trench isolation techniques that are well known in theart including, for example, forming a patterned mask on the surface ofthe substrate via lithography, etching a trench into the substrate thruan opening in the patterned mask, filling the trench with a trenchdielectric such as SiO₂ or TEOS and planarizing the structure. Anoptional trench liner can be formed within the trench prior to trenchdielectric fill and an optional densification step may follow theplanarization process.

Prior to forming the gate dielectric 22, the surface of substrate 12 iscleaned to remove any residual layers (e.g., native oxide), foreignparticles, and any residual metallic surface contamination and totemporarily protect the cleaned substrate surface. Any residual siliconoxide is first removed in a solution of hydrofluoric acid. The preferredremoval of particles and residual metallic contamination is based on theindustry standard gate dielectric preclean known as RCA clean. The RCAclean includes a treatment of the substrate 12 in a solution of ammoniumhydroxide (NH₄OH) and hydrogen peroxide (H₂O₂) followed by an aqueousmixture of hydrochloric acid and an oxidizing agent (e.g., H₂O₂, O₃). Asa result, the cleaned substrate surface is sealed with a very thin layerof chemical oxide (not shown). While the protective chemical oxide istypically made thinner than about 10 Å so to not interfere with theproperties of gate dielectric 22, its thickness can be varied tobeneficially alter properties of the gate dielectric 22.

A blanket layer of gate dielectric 22 is formed on the entire surface ofthe structure 10 including the semiconductor substrate 12 and atop theisolation region 34, if it is present and, if it is a depositeddielectric. The gate dielectric 22 can be formed by a thermal growingprocess such as, for example, oxidation. Alternatively, the gatedielectric 22 can be formed by a deposition process such as, forexample, chemical vapor deposition (CVD), plasma-assisted CVD, atomiclayer or pulsed deposition (ALD or ALPD), evaporation, reactivesputtering, chemical solution deposition or other like depositionprocesses. The gate dielectric 22 may also be formed utilizing anycombination of the above processes.

The gate dielectric 22 is comprised of an insulating material having adielectric constant of about 4.0 or greater, preferably greater than7.0. The dielectric constants mentioned herein are relative to a vacuum,unless otherwise stated. Note that SiO₂ typically has a dielectricconstant that is about 4.0. Specifically, the gate dielectric 22employed in the present invention includes, but is not limited to: anoxide, nitride, oxynitride and/or silicates including metal silicates,aluminates, titanates and nitrides. In one embodiment, it is preferredthat the gate dielectric 22 is comprised of an oxide such as, forexample, SiO₂, HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃ andmixtures thereof.

The physical thickness of the gate dielectric 22 may vary, buttypically, the gate dielectric 22 has a thickness from about 0.5 toabout 10 nm, with a thickness from about 0.5 to about 2 nm being moretypical.

After forming the gate dielectric 22, a blanket layer of polysilicon oranother gate conductor material or combination thereof, which becomesthe gate conductor 24 shown in FIG. 1, is formed on the gate dielectric22 utilizing a known deposition process such as, for example, physicalvapor deposition, CVD or evaporation. The blanket layer of gateconductor material may be doped or undoped. If doped, an in-situ dopingdeposition process may be employed in forming the same. Alternatively, adoped gate conductor layer can be formed by deposition, ion implantationand annealing. The doping of the gate conductor layer will shift theworkfunction of the gate formed. Illustrative examples of dopant ionsinclude As, P, B, Sb, Bi, In, Al, Ga, Tl or mixtures thereof. Typicaldoses for the ion implants are 1E14 (=1×10¹⁴) to 1E16 (=1×10¹⁶)atoms/cm² or more typically 1E15 to 5E15 atoms/cm². The thickness, i.e.,height, of the gate conductor 24 deposited at this point of the presentinvention may vary depending on the deposition process employed.Typically, the gate conductor 24 has a vertical thickness from about 20to about 180 nm, with a thickness from about 40 to about 150 nm beingmore typical.

The gate conductor 24 can comprise any conductive material that istypically employed as a gate of a CMOS structure. Illustrative examplesof such conductive materials that can be employed as the gate conductor24 include, but are not limited to: polysilicon, conductive metals orconductive metal alloys, conductive silicides, conductive nitrides,polySiGe and combinations thereof, including multilayers thereof. Insome embodiments, it is possible to form a barrier layer betweenmultiple layers of gate conductors.

An optional dielectric cap (not shown) can be formed atop the gateconductor 24 at this point of the present invention. The optionaldielectric cap is typically removed before or immediately after thesource/drain regions to be subsequently formed have been silicided.

The blanket gate conductor 24 and the gate dielectric 22 are thenpatterned by lithography and etching so as to provide at least onepatterned gate stack. When a plurality of patterned gate stacks arepresent, the patterned gate stacks may have the same dimension, i.e.,length, or they can have variable dimensions to improve deviceperformance. Each patterned gate stack at this point of the presentinvention includes at least the gate conductor 24 and the gatedielectric 22. The lithography step includes applying a photoresist tothe upper surface of the gate conductor 24, exposing the photoresist toa desired pattern of radiation and developing the exposed photoresistutilizing a conventional resist developer. The pattern in thephotoresist is then transferred to the blanket layer of gate conductor24 and the gate dielectric 22 utilizing one or more dry etching steps.In some embodiments, the patterned photoresist may be removed after thepattern has been transferred into the blanket layer of gate conductor24.

Suitable dry etching processes that can be used in the present inventionin forming the patterned gate stacks include, but are not limited to:reactive-ion etching, ion beam etching, plasma etching or laserablation. A wet or dry etching process can also be used to removeportions of the gate dielectric 22 that are not protected by thepatterned gate conductor 24.

Next, an offset spacer 26 is formed on exposed sidewalls of eachpatterned gate stack. The offset spacer 26 is comprised of an insulatorsuch as an oxide, nitride, oxynitride, or carbon-containing siliconoxide, nitride, oxynitride, and/or any combination thereof. Preferably,the offset spacer 26 is comprised of an oxide or an oxynitride. Theoffset spacer 26 can be formed by deposition and etching or by thermaltechniques. The width of the offset spacer, as measured at the surfaceof substrate 12, is narrower than that of the outer spacers 28 to besubsequently formed. Typically, offset spacer 26 has a width from about2 to about 100 nm, with a width from about 5 to about 15 nm being evenmore typical.

After providing the offset spacer 26, source/drain extension regions 18are formed utilizing a conventional extension ion implantation process.An optional anneal process may follow the extension ion implant. In someembodiments, a halo implant (not shown) can be formed at this point ofthe inventive process utilizing a conventional halo ion implantationprocess.

Next, at least one outer spacer 28 which is comprised of a differentinsulating material as the offset spacer 26, preferably a nitride, isformed by deposition and etching. The at least one outer spacer 28 mustbe sufficiently wide enough such that the source and drain silicidecontacts (to be subsequently formed) do not encroach underneath theedges of the gate stack. Typically, the source/drain silicide contactsdoes not encroach underneath the edges of the gate stack when the atleast one outer spacer 28 has a width, as measured at the bottom, fromabout 15 to about 200 nm.

After outer spacer 28 formation, source/drain diffusion regions 16 areformed into the substrate 12. The source/drain diffusion regions 16 areformed utilizing ion implantation and an annealing step. The annealingstep serves to activate the dopants that were implanted by the previousimplant step (or steps if annealing was not previously been performed toactivate the dopants within the extension implant regions). At thispoint of the present invention, a buffer implant may be performed toprovide the source/drain regions with a graded junction that optimizesthe series resistance of the device.

In some embodiments of the present invention and when the substrate 12does not include silicon, a Si-containing layer can be formed atop ofthe exposed portions of the substrate 12 to provide a source for formingthe silicide contacts. Illustrative examples of Si-containing materialsthat can be used include, for example, Si, single crystal Si,polycrystalline Si, SiGe, and amorphous Si. This embodiment of thepresent invention is not illustrated in the drawings.

Next, the source/drain diffusion regions 14 and optionally the gateconductor 24 are silicided utilizing a standard salicidation(‘self-aligned’) process well known in the art. This includes forming ametal capable of reacting with Si atop the entire structure, forming abarrier layer atop the metal, heating the structure to form a silicide,removing non-reacted metal and the barrier layer and, if needed,conducting a second heating step. The second heating step is required inthose instances in which the first heating step does not form the lowestresistance phase of the silicide. In FIG. 1, reference numeral 30denotes the silicided source/drain regions. Note that if the gateconductor 24 is comprised of polysilicon or SiGe and no dielectric capis present, this step of the present can be used in forming a metalsilicide 32 atop the gate conductor 24. The latter embodiment isspecifically shown in the drawings of the present application.

Next, and as illustrated in FIG. 2, the outer spacer 28 is removed fromthe structure utilizing an isotropic etching process that selectivelyremoves the outer spacer 28, without substantially removing offsetspacer 26. It is noted that this selective etching step is dependant onthe compositions of the outer spacer 28 and the offset spacer 26. Forexample, when the outer spacer 28 is comprised of a nitride, and theoffset spacer 26 is comprise of an oxide or oxynitride, HF can be usedin removing the nitride outer spacer. Alternatively, and in the specificembodiment illustrated, a dry etching process such as reactive-onetching containing a gas including F, O, C and N atoms in He can be usedin removing the outer nitride spacer 28. As shown in FIG. 2, the removalof the outer spacer 28 exposes a surface portion of the semiconductorsubstrate 12 including the source/drain extension regions 18. Theexposed surface portion is labeled as 35 in FIG. 2.

FIG. 3 shows the structure of FIG. 2 after performing a selectiveplating process which forms a metallic or intermetallic material 36 onthe exposed surface portions 35 of at least the source/drain extensionregions 18 and optionally on the silicide contacts 30 and 32. Theselective plating process is performed utilizing plating techniques thatare well known in the art. For example, both electroplating andelectroless plating are contemplating herein. Preferably, the platingtechnique used in the present invention comprises electroless plating.

Metal deposition by electroless plating is well practiced in industry.In electroless deposition process, a redox reaction involving theoxidation of one or more soluble reducing agent(s) and the reduction ofone or more metallic ions occurs on the surface of a substrate. For manymetals including Cu, Ni, Co, Au, Ag Pd, Rh, the freshly depositedsurface is sufficiently catalytic for the process to continue. To beginthe process, however, the substrate is first seeded with a thin layer ofcatalytic material such as palladium to initiate the electrolessdeposition. More commonly, the substrate is primed with a palladium ioncontaining solution. Palladium ion undergoes an immersion exchangereaction with the substrate leading to formation of a thin layer (1 to afew mono layer thick) of palladium. For example, for plating of CoWPover copper features in a semiconductor device, the wafer is primed witha dilute solution of palladium acetate.

Palladium ions reacted with copper and reduced to palladium metal whilethe Coulombic equivalent amount of copper was etched out as copper ions.Wafer is well rinsed with water containing complexing agent such as EDTAto remove extraneous palladium to avoid bridging in subsequent plating.Background information on electroless plating are well documented inIndustrial Electrochemistry—D. Pletcher and F. C. Walsh (Editor), 2^(nd)Edition, Chapman and Hall, NY, 1990, ISBN: 0412304104 and ElectrolessPlating: Fundamentals and Applications—G. O. Mallory, J. B. Hajdu(Editor) 1990, ISBN: 0815512775.

Palladium seeding by immersion displacement works only on substrate withfeatures that are active to undergo an exchange reaction with thepalladium ion in solution. In principle, selective plating is achievedby prior defining the area to be plated with a suitable material such ascopper, then apply a suitable seeding followed by plating, asexemplified in U.S. Pat. No. 4,877,644 where the general area is maskedwith polymeric plating resist, followed by selective removal of resistat a selective area to expose the underlying metal and finished withelectroless plating. An alternative approach is to do selective seedlingby forming defined features of palladium or other seeding material firstupon which electroless plating is taken place. “Selective Plating ofCopper for Circuitzation of Teflon and Epoxy based Substrates”, T. H.Baum et al., Proceedings of Electrochemically Deposited Thin Films II,Fl, USA, 1994, p 320-7 provides a technique to incorporate potassiumiron (III) oxalate in the presence of palladium(II) chloride andselectively forming palladium metal features upon which metal conductionare plated by exposure to UV light. U.S. Pat. No. 5,260,108 describesselective seeding using an excimer laser radiation. A circuit repairtechnique using laser to heat up a local area to accelerate palladiumseeding leading to selective copper plating was documented in “CircuitRepair Using Palladium Seeding and Selective Electroless Plating”,Vigliotti, D R et al., IBM Technical Disclosure Bulletin, v37 n6B 06-94p 443-444.

Another example of using photoexcitation to modified a surface toachieve selective plating is mentioned in “Development of PhotoexcitedSurface Modification Technology Utilizing Modulator Radiation”, Y.Tsutsui et al., Sumitomo Electric Industries Tech. Rev. (Japan), No. 45,January 1998, p 169-74.

In electroless plating, activation of a surface, non conductive, orsemiconductor can be achieved by the incorporation onto the top surfacelayer of nanometer sized catalytic particles. These catalytic particlescan be either Pd, Co, Ni, and they can be applied by a either physicalor chemical deposition.

The function of these particles is to catalyze and initiate theelectrochemical deposition reaction when the substrate is immersed intoan electroless plating bath. The electroless plating bath deposits aconductive layer on the catalyzed area of the substrate, the thicknessof the plating layer depending mainly on the time of exposure to theplating bath. A suitable electroless plating system used in thisinvention is based on the use of the hypophosphite reducing agent. Inthis system, a mixture of hypophosphite ions and cobalt or nickel ionsis made together with

citrate stabilizing agent, at a suitable pH and temperature (usuallybetween 65° to 75° C.). When the activated catalyzed substrate describedabove is immersed on this plating bath, the following reaction occurs onthe substrate:

The Co metal is then deposited selectively on top of the catalyzed Pdlayer on the substrate. The metal deposited by this reaction, can beeither CoP, or NiP, or CoWP, or NiWP, CoB or NiB or CoWB, depending onthe composition of the plating bath solution. The catalytic layer can beeither Pd, or Ni or Co metal. The catalytic Pd layer can be incorporatedon the surface of the substrate either by ion implantation, or othertype of physical deposition method, or it can be applied by chemicalmeans. For example, a colloidal Pd catalytic solution containingmicroparticles of Pd in suspension can be injected in the inside of thetrench cavity and it will deposit the Pd particles with very goodadhesion onto the inside of the trench wall. To make the catalyticprocess selective, in a later step as described below, the catalyticlayer is removed selectively from unwanted areas.

As stated above, the selective plating process forms a metallic orintermetallic material 36 on the locations previously mentioned. Themetallic or intermetallic material 36 comprises a low-resistancematerial such as, for example, W, Al, Cu, Au, Pt, Pd, Ni, Co, Re, Rh,Ag, TiN, Ti, TaN, WN or alloys, including silicon-containing alloysthereof In one embodiment of the present invention, the metallic orintermetallic material 36 comprises CoWP. By ‘low-resistance’, it ismeant that material 36 has a resistivity that provides an extensionconnection having a resistance of less than 50 ohms/square. Thethickness of the metallic or intermetallic material 36 may varydepending on the conditions used for plating the same. Typically, themetallic or intermetallic material 36 has a thickness from about 1 toabout 20 nm, with a thickness from about 2 to about 5 nm being moretypical. The metallic or intermetallic material 36 located above theexposed portions 35 of the extension regions 18 forms a low-resistanceextension connection between the MOSFET channel and the silicidedcontacts 30 located above the source/drain regions 16, i.e., thesilicided source/drain regions.

FIG. 4 shows the structure after forming a liner 38 over the structureshown in FIG. 3. The liner 38 is optional and is not required in allinstances. The liner 38 is formed by a conventional deposition processsuch as, for example, chemical vapor deposition, plasma enhancedchemical vapor deposition, chemical solution deposition, evaporation andother like deposition processes. The liner 38 is comprised of a materialthat is capable of introducing stress into the channel region of thestructure. For example, liner 38 may be comprised of a nitride that isunder either tensile or compressive stress. The liner 38, when present,typically has a thickness from about 10 to about 500 nm, with athickness from about 10 to about 50 nm being even more typical.

At this point of the present invention conventional back-end-of-the-line(i.e., interconnect) technology can be used in forming contacts to thesilicided source/drain regions and optionally the silicided gateconductor.

Although specific mention of the above processing is made, the presentinvention can also be implemented into a replacement gate process byfirst providing the structure shown in FIG. 1 by a conventionalreplacement gate process and then following the description provided forFIGS. 2-4.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A method of fabricating a semiconductor structure comprising:providing a structure that at includes at least one gate region locatedon a surface of a semiconductor substrate, said at least one gate regioncomprising source/drain regions and source/drain extension regions insaid semiconductor substrate that are separated by a channel region, agate dielectric and a gate conductor located above said channel region,an offset spacer located on sidewalls of at least said gate conductorand an outer spacer adjacent said offset spacer and silicide contactslocated atop the source/drain regions adjacent said outer spacer;removing said outer spacer to expose a surface portion of thesemiconductor substrate including said source/drain extension regions;and selectively plating a metallic or intermetallic material on saidexposed surface portion of said semiconductor substrate including saidsource/drain extension regions.
 2. The method of claim 1 wherein saidproviding said structure comprises deposition, lithography and etchingor a replacement gate process.
 3. The method of claim 1 wherein saidremoving of said outer spacer is performed by a selective isotropicetching process.
 4. The method of claim 3 wherein said selectiveisotropic etching comprises HF as a chemical etchant.
 5. The method ofclaim 3 wherein said selective isotropic etching comprises reactive-ionetching using a gas containing F, O, C and N.
 6. The method of claim 1wherein said selectively plating is by electroless plating.
 7. Themethod of claim 1 wherein said selectively plating is by electroplating.
 8. The method of claim 1 wherein said metal or intermetallicmaterial extends on and covers exposed surfaces of said silicidecontacts.
 9. The method of claim 1 wherein said metallic orintermetallic material comprises W, Al, Cu, Au, Pt, Pd, Ni, Co, Re, Rh,Ag, TiN, Ti, TaN, WN or alloys thereof.
 10. The method of claim 1wherein said metallic or intermetallic material comprises CoWP.
 11. Themethod of claim 1 further comprising forming a liner that introducesstress into said channel region, said liner is located over saidsemiconductor substrate including said silicide contacts, said metallicor intermetallic material, said gate dielectric and said gate conductor.